The subject matter disclosed herein relates to integrated circuit devices. More particularly, the subject matter relates to Silicon on Insulator (SOI) devices including subsurface wires, and methods of forming subsurface wires therein.
As integrated circuit (IC) technologies have advanced, the size of these devices has correspondingly decreased. In particular, as devices are reduced in scale to comply with ever-smaller packaging, tighter constraints are applied to their dimensions and spacings.
As device dimensions are reduced, the line resistance and via resistance within an IC can increase, causing signal propagation delays, and reduced performance of that IC. In SOI devices, the formation of traditional interconnects can be difficult, and may cause noise, thermal increases, and other interference.